This application relates generally to processing systems, and, more particularly, to checkpointing registers for transactional memory in processing systems.
Conventional processor-based systems typically include one or more processing elements such as a central processing unit (CPU), a graphical processing unit (GPU), an accelerated processing unit (APU), and the like. The processing units include one or more processor cores that are configured to access instructions or data that are stored in a main memory and then execute the instructions or manipulate the data. The state of the processing units or the processor cores can be defined, at least in part, by values stored in a set of architectural registers. For example, instruction set architectures (ISA) may support a set of named architectural (or micro-architectural) registers that can be used in software created for the machine. The set of architectural registers may include 48 registers: 16 integer registers and 32 floating-point registers.
The processing units or processor cores also implement a set of physical registers in a physical register file. The physical registers may be used to store different types of information during operation of the processing unit or processor cores. For example, physical registers may be used to store data for in-flight operations until this data is committed to the state of the machine. The architectural registers can be mapped to the physical registers in the physical register file, e.g., using renaming logic that maps the name of the architectural register to a physical register number that identifies a physical register. In operation, the physical registers can be allocated to in-flight operations or architectural registers as needed, depending on the availability of the physical registers in the physical register file.
Transactional memory is implemented in computer architectures that support parallel programming. Programmers can define a group of instructions as a transaction and the instructions in the transaction are executed in an atomic and isolated way. Instructions in an atomic transaction are executed as a block with respect to all other concurrent execution threads. The instructions in a transaction are isolated so that intermediate results produced by the transaction are not exposed to the rest of the system until the transaction completes. However, transactions do not always successfully complete and may be aborted before completion. In these cases, the state of the machine is rolled back to a state corresponding to a checkpoint that is defined for the transaction. A transaction checkpoint may be defined, at least in part, by the state of registers in the machine prior to executing instructions in the transaction. The register state may be defined by the values stored in architectural registers, physical registers, or a rename file that indicates the relations between the architectural and physical registers.